Many semiconductor memory devices use one or more internal clock signals to, for example, control operations of the device. These internal clock signals may be generated from one or more external clock signals. However, the performance of certain circuits within the semiconductor memory device may be impacted by the frequency of the clock signals that are used. As such, it may be desirable to have circuits in a semiconductor device operate in one way when a clock signal having a first frequency is used and act in a different way when a clock signal having a different frequency is used.
For example, when a delay locked loop (DLL) is used to generate an internal clock signal that is synchronized with an external clock signal, the internal clock signal typically can be synchronized with the external clock signal even if the delay circuit has a short delay time, so long as the external clock signal has a high frequency. However, a delay circuit having a relatively long delay time should be used to synchronize the internal clock signal with the external clock signal when the external clock signal has a low frequency.
In conventional semiconductor memory devices, a CAS latency (CL) value that is set, for example, by a user of the device may provide information about the frequency of the external clock signal. FIG. 1 is a block diagram of a circuit that may be used in a conventional semiconductor memory device to generate an internal clock signal from an external clock signal. The circuit of FIG. 1 provides for different delays that may be implemented based on the frequency of the external clock signal.
As shown in FIG. 1, first and second delay circuits 10 and 12, which are selected by a CAS Latency (CL) value, may be used to delay an input signal IN (i.e., the external clock signal that is to be used to generate the internal clock signal) by different predetermined amounts. The first and second delay circuits 10 and 12 output the delayed input signal as an output signal OUT. In conventional semiconductor memory device, the CL value is set based on the frequency of the input clock signal. Thus, the circuit of FIG. 1 varies the amount which the external clock signal is delayed to produce the internal clock signal based on the frequency of the external clock signal as reflected by the CL value. Accordingly, when a CL value is set by the user in response to the frequency of the external clock signal, the circuit illustrated in FIG. 1 can generate the output signal OUT at a different time by selecting one of the first delay circuit 10 and the second delay circuit 12 in response to the CL value.
FIG. 2 is a block diagram illustrating a method of adjusting the delay time of a delay circuit in response to the frequency of an external clock signal in a DLL of a conventional semiconductor memory device. In the delay circuit of FIG. 2, each of the third and fourth delay circuits 20 and 22 may be composed of one or more delay elements. The third and fourth delay circuits may have the same, or different, delay times.
As noted above, a DLL is often used to synchronize the internal clock signal with the external clock signal in a semiconductor memory device. As also discussed above, the internal clock signal can typically be synchronized with the external clock signal even when the DLL has a short delay time if the input clock signal has a high frequency. However, the DLL may need to have a relatively long delay time if the input clock signal has a low frequency.
In the DLL circuit of FIG. 2, the CL value set by the user may be used to set/cut the first and second fuses 24 and 26. When the frequency of the clock signal is relatively high, the CL value may be chosen so that only the second fuse 26 is cut, so that the internal clock signal will be generated by the third delay circuit 20, and the fourth delay circuit 22 is not used. In this manner, the delay time associated with the delay circuit is relatively shorter. In contrast, when the frequency of the clock signal is relatively low, the CL value may be chosen so that neither the first fuse 24 nor the second fuse 26 are cut. As a result, the internal clock signal is generated through both the third delay circuit 20 and the fourth delay circuit 22, thereby making the delay time relatively longer.
As the CL value may be used to convey information about the frequency of the clock signal, the CL value may need to be changed if the frequency of the clock signal that is to be input to the semiconductor memory device is changed. If the CL value is not set correctly by the user, the semiconductor memory device may not work properly.